1. Field of the Invention
The embodiments of the invention generally relate to hybrid-orientation technology (HOT) wafers and, more particularly, to a trench isolation structure for patterning devices on a HOT wafer and an associated method for forming the trench isolation structure using a non-selective etch.
2. Description of the Related Art
Typically, device patterning on silicon-on-insulator (SOI) wafers is accomplished using shallow trench isolation structures formed with a selective silicon etch chemistry that stops on the top surface of a buried oxide (BOX) layer. Unfortunately, application of this selective STI etch process to form shallow trench isolation structures on hybrid-orientation technology (HOT) wafers and, particularly, on HOT wafers at the 45 nm or smaller technology creates very small trench features at the bulk/SOI interface. This is due to overlay (OL) tolerances between the STI lithography pattern and the underlying bulk/SOI pattern. Specifically, the problem is that the resulting STI feature formed in the bulk silicon is trimmed by the buried-oxide layer of the SOI portion, which is below the ground rule and would likely exceed the STI oxide fill capability for the technology node. There is no known solution in practice since current silicon integration uses either bulk or SOI substrates.